1. Field
The present invention relates to integrated circuits and, more particularly, to systems and methods for power reduction using multi-domain heterogeneous process-voltage-emperature tracking.
2. Background
The increased use of mobile, battery-powered devices has increased the importance of reducing power consumption in large heterogeneous system-on-a-chip integrated circuits (SoCs). Among the techniques to achieve power reductions, dynamically adjusting supply voltage based on tracking process, temperature, and voltage drop is highly effective since reducing supply voltage can significantly reduce both dynamic and static power of an SoC.
However, in large SoCs with many millions of transistors on a single die, there are several supply domains that can have independent voltage levels. Additionally, an SoC can have a number of heterogeneous devices, for example, transistors with different threshold voltages (Vth) and channel lengths, with each type of device having its own performance and power attributes. Dynamically adjusting supply voltages for a whole SoC can also be very difficult due to the use of (1) different technology library implementations such as high-speed and high-density; (2) different supply domains with different configurations of voltage regulators (e.g., using a switching mode power supply (SMPS) or low drop-out (LDO) regulator); and (3) a variety of hard macros that can each have a different supply domain and independent power controls.
Limitations of prior approaches include high complexity, difficult to adapt to new designs, cost (power and chip area), and lost performance. A prior approach to track all these supply domains with heterogeneous hard macros and technology library implementations is Process Voltage Scaling (PVS). This is a traditional approach that determines the process conditions of the die. It is based on binning using Fmax (maximum operating frequency) vectors during production testing. Limitations of PVS include: not able to track temperature; high cost of test time; process binning is coarse grained; difficult to track heterogeneous domains and hard macros; determining a good Fmax vector on complex SoCs is very difficult; and cannot compensate for board-level drops on supply voltages.
A second prior approach to track all these supply domains with heterogeneous hard macros and technology library implementations is open loop voltage adjustment using process monitors where several PVT (process, voltage, temperature) monitors can be placed in each supply domain and read during chip testing to determine the die process conditions (e.g., slow, nominal, fast). The appropriate voltage for each supply domain can be stored (e.g., by blowing fuses) during the testing process based on measurements from the process monitors. This approach, compared to PVS, has better test time and less complexity, does not need Fmax vectors, and can be used with heterogeneous domains. Limitations of this second prior approach include that it can only track process variation and thus requires added margins (that reduce device performance) for temperature and other factors.
A third prior approach to track all these supply domains with heterogeneous hard macros and technology library implementations combines the process monitors of the above approach with PVT monitors and uses a central controller for each supply domain and each device type to dynamically adjust voltage during operation of the SoC. This approach can lower power consumption of the open-loop approaches due to the additional supply voltage adjustments. However, this approach needs PVT monitors in each power and supply domain and a central controller per each supply domain or sub-regulated domain and per each library implementation type. These central controllers read the data of PVT monitors, interpret the data, and send voltage recommendations for their domains to an arbiter (e.g., a hardware or software based power management integrated circuit (PMIC) controller).
Limitations of this third approach include the power and area overhead due to the use of multiple central controllers—for each supply domain and each library implementation. This overhead can be very large since the number of supply domains in complex SoCs is large. The overhead could wipe out the power savings. Also, this approach is also complex. For example, managing the supply voltage in just a single supply domain with different technology library implementations and with different device types is difficult.